In order to meet higher and higher chip performance (speed) and density objectives, for the submicron era, increasing attention has been placed on interconnect technology. This concern applies to multilevel interconnects as well as to the more localized device connections and device interconnects, which are the subject of this invention. As device dimensions progress down into the sub-quarter-micron regime, the performance benefits of continued shrinkage will not be fully realized unless device contact resistance and local device interconnect line resistance is continually reduced. Historically, such reductions have resulted from innovative ways to lower the sheet resistance of doped polysilicon layers, while still retaining the benefits of polysilicon gates and local polysilicon lines. Some of the benefits of polysilicon layers have been and continue to be: (1) Well controlled FET device threshold voltages, when used as gate electrodes and (2) the ability to be readily oxidized for purposes of electrical insulation. However, since the advent of the sub-micron era, the interconnect delays, associated with polysilicon have become too large, relative to inherent device switching times. Accordingly, the industry has largely addressed this problem by using refractory metals (such as: Titanium, Ti, and Tungsten, W), in conjunction with polysilicon, in order to form silicide layers with resistivities at least 20 times lower than that of highly doped polysilicon. Currently, such silicide layers (polycides) are a basic building block in evolving implementations of the Self-Aligned Silicide (Salicide) Technology.
In a typical salicide device structure, a gate oxide layer and an overlying polysilicon layer are first patterned into gate regions. The gate regions are then covered by an overlying oxide layer and then subsequently etched back, anisotropically, in order to form exposed source-drain regions and exposed polysilicon gate regions that are self-aligned and laterally separated by rounded oxide spacers on both ends of the gate. Following an ion implantation step for doping the source-drain and polysilicon gate region, a blanket layer of Ti, for example, is deposited and then thermally reacted in order to form Titanium Silicide, TiSi.sub.2, on gate and source-drain regions. The unreacted titanium, over the spacers, etc., is then chemically removed.
The above Ti-Salicide process, including Lightly Doped Drain (LDD), etc., derivatives thereof, has been a key driving force behind current manufacturing efforts for high-speed CMOS devices. To cite just a few reasons, it has been very successful, in terms of providing the low resistivity gate and source-drain regions needed for high, speed signal propagation, while retaining the very desirable threshold voltage control and oxidizable aspects of polysilicon.
However, this technology has run into problems as device dimensions have continued to shrink into the sub-quarter-micron range. For example, TiSi.sub.2 exhibits a line width effect due to the kinetic restriction imposed on the C49-to-C54 phase transformation by shrinking polysilicon gate lengths. This results in increased gate sheet resistance as the gate length increases. The reason for this is that for the C54-polymorph as the C49-grain size becomes comparable with the gate lengths. These nucleation sites are essentially C49-TiSi.sub.2 triple grain boundaries.
It has also been observed that as the gate length continues to shrink, the increased lateral stress due to the spacers on the narrow gates contributes to non-uniform silicide layers on the gates. In addition, voids have been observed in TiSi.sub.2 films formed on highly BF.sub.2 -implanted polysilicon, presumably due to a combination of factors, such as: (1) Residual polymers resulting from nitride spacer effect etching, (2) Dopant effects, (3) line width effects and (4) Increased lateral stress on narrow gates. The present invention addresses these problems.
In addition to the above problems, addressed by the present invention, shrinking device dimensions have also resulted in a number of other problems that have been addressed in the prior art.
As device dimensions have continued to shrink, even the much lower sheet resistances of TiSi.sub.2, relative to doped polysilicon, have become a performance limitation and this has necessitated additional innovation for further reductions in sheet resistance. It has been found that the sheet resistance of a silicide can be further reduced by using an ion implant process to amorphize the polysilicon layer, prior to forming TiSi.sub.2. It has also been found that cobalt and nickel silicides can provide lower sheet resistances than that of Titanium silicide. However, such innovations have also been found to have their own problems, which have been addressed in the following patent by Wong, et. al.
U.S. Pat. No. 5,731,239, to Wong, et. al., teaches an improved and simplified method for lowering the sheet resistance of gate electrodes by means of a pre-amorphization ion implant, prior to titanium silicide formation, as well as by the use of cobalt silicide. A self aligned additional insulating layer is used to mask the source-drain regions during the ion implant process for pre-amorphization of the gate electrode. A Chemical Mechanical Polishing, CMP, process is used as part of the process to form the aforementioned self aligned insulator mask, which saves a photolithography step. This invention, however, does not address the above mentioned stress problems, associated with narrow salicide gates.
The conventional salicide process technology, described above, is also prone to so-called trenching problems that can become more severe as device dimensions get smaller. During the anisotropic etching that is used to form the polysilicon gate electrode, there is a risk of penetrating the surrounding thin gate oxide, where the source drain regions will eventually be formed.
U.S. Pat. No. 5,688,704, to Liu, teaches a method to avoid the above trenching problem. A T-shaped polysilicon gate is used, whereby the outer winged-portion of the T-shaped gate is resting on a thick insulator. Therefore, the underlying surface is well protected during a subsequent anisotropic etch back step which forms the gate. During the same etch back step, rectangular spacers are formed under the winged edges of the T-shaped gate. These rectangular spacers help to prevent bridging between the gate and source-drain regions after the eventual silicide formation step. Since the T-shaped gate has more relative vertical and lateral surface area for salicidation, it should help to reduce stress. However, the increased device area required for T-shaped gates is not compatible with shrinking design rules for most sub-quarter-micron needs.
U.S. Pat. No. 5,196,357, to Boardman, et. al., also teaches a method for improving the performance and reliability of CMOS FET devices, using Self-Aligned Silicide (Salicide) Technology. As in the case of the above patent, to Liu, the concern over plasma etch damage to surrounding source-drain regions, during the conventional formation of the polysilicon gate electrode, is addressed. Also, similar to the above patent, to Liu, a T-shaped gate is also used. Again, the greater vertical and lateral surface area of the T-shaped gate would tend to reduce the stress problems addressed by the present patent but the associated increased device area would not be compatible with shrinking design ground rules.